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ISL6720A
Data Sheet August 23, 2007 FN6487.1
100V Triple Linear Bias Supply
The ISL6720A is a low cost linear regulator for generating a low voltage bias supply from intermediate distributed voltages commonly used in telecom and datacom applications. It produces three separate outputs, an adjustable 0V to 20V output rated at up to 125mA which can be back-biased from an external source such as an auxiliary transformer winding, a 50mA switched regulated output adjustable between 0V and 15V, and a fixed continuous 5V output rated at 25mA. The ISL6720A may be used as a start-up or a continuous low power regulator. When operating as a start-up regulator, it is capable of sourcing over 100mA from a 100V source for short durations. This period of time allows the power supply to start-up and provide a low voltage alternate power source, such as the output of a transformer winding, to the VIO output. This allows the remaining outputs to be operated from a lower source voltage thereby minimizing power loss.
Features
* 100V Input Capability * Adjustable Auxiliary Winding Regulator with 40V Withstand Capability * Up to 125mA Combined Output Current on Switched and Unswitched Outputs * 250s Delayed Start (VIO, VSW) after Continuous (VCONT) Output * Regulated Switched (VSW) and Unswitched Outputs (VIO) * 5V @ 25mA Continuous Output (VCONT) * 2-Stage Over-Temperature Protection * Package Compliant with IPC2221A, Creepage and Clearance Spacing Requirements * Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE (C) -40 to +105 PACKAGE (Pb-Free) 11 Ld DFN PKG. DWG. # L11.4x4
Applications
* Telecom/Datacom DC/DC Converters * Low Power Bias Supplies
ISL6720AARZ* 67 20AARZ
Pinout
ISL6720A (11 LD DFN) TOP VIEW
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VPWR
1
11 VIO 10 NC
VCONT VCOMP GND VSWADJ
2 3 4 5
9 8 7 6
VADJ VSW VSWCOMP ENABLE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VADJ
INPUT SELECTOR
VIO
2
VPWR START/STOP UV COMPARATOR VPWR OK + - +140C TEMP OK BG + GND MAIN ENABLE HIGH VOLTAGE REGULATOR INPUT SELECTOR IN OUT VSW VSWCOMP VSWADJ POST REGULATOR
ISL6720A
+150C TEMP OK 2-LVL TMON +140C 10C +150C 10C VCONT ENABLE ENABLE VCONT IN OUT VCOMP
POST REGULATOR
POR
250s DELAY
+ + -
FALLING EDGE DELAY
FN6487.1 August 23, 2007
Typical Application
CONVERTER POWER STAGE
VIN+
+VOUT
3
VINRETURN
ISL6720A
1 C2 1.0nF 2 3 4 5
VPWR
VIO 11 N/C 10
R1*
PWM
FEEDBACK AMPLIFIER
VCONT VCOMP
VADJ 9 VSW 8 C3 220pF -CONTROLLER
GND VSWCOMP 7 VSWADJ ENABLE 6
C1 1.0F
U1 ISL6720A
C4 1.0F
*SIZED FOR MINIMUM ZENER BIAS CURRENT
FN6487.1 August 23, 2007
ISL6720A
Absolute Maximum Ratings (Note 3)
Supply Voltage, PWR. . . . . . . . . . . . . . . . . . . . GND -0.3V to +105V VIO, VADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +40V VSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +23V All others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +6.0V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 11 Ld DFN . . . . . . . . . . . . . . . . . . . . . . 36 2.0 Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL6720AARZ. . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C Supply Voltage Range (Typical). . . . . . . . . . . . . . 18VDC to 80VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2 and "Typical Application" on page 3. 17 V < VPWR < 100V, CVSW = CVCONT = 1F, IVCONT = -250A, IVSW = -500A, VSW Enabled, TA = -40C to +105C (Note 4), Typical values are at TA = +25C TEST CONDITIONS MIN TYP MAX 100 VPWR = 12V VSW Enabled, VPWR = 100V IVIO = 0 VSW Disabled, VPWR = 100V, IVIO = 0 VIO Biased Externally at 40V, VSW Enabled, VPWR = 100V IVSW = -50mA, IVCONT = -25mA 320 1.3 1.2 1.2 470 1.7 1.7 1.7 UNITS V A mA mA mA
PARAMETER SUPPLY VOLTAGE, VPWR Supply Voltage Start-Up Current, IPWR Operating Current, IPWR
UVLO START Threshold UVLO STOP Threshold Hysteresis OUTPUT VOLTAGE VIO Overall Accuracy
VADJ = VSWADJ = 0V, IVCONT = 0mA, VSW Disabled VADJ = VSWADJ = 0V, IVCONT = -1mA, VSW Disabled UVLO START to UVLO STOP IVIO = 0mA to -125mA , VADJ = 10V, 20V, VPWR = 48V VSW Disabled IVIO = 0mA to -10mA , VADJ = 10V, 20V, VPWR = 48V VSW Disabled
12.4 11.5 0.8 VADJ - 4.5 1.2
16.9 15.3 1.7 VADJ - 0.5
V V V V
VADJ - 3.5
VADJ - 0.5
V
Setpoint Range
VPWR = 48V, VSW Disabled, IVIO = 0mA for minimum setpoint IVIO = -125mA for max setpoint VPWR - VIO, minimum VPWR = 17V, 100V VADJ = 20V, IVIO = -125mA VIO final = 0.95 x VIO initial VPWR = 48V, 100V VADJ = 40V, VSW Disabled, IVIO = 0mA VPWR = 12V, IVADJ = 10mA VPWR = 17V, 100V VADJ = 15V, VSW Disabled VIO remains greater than 10.5V
0.5
20.0
V
Source Voltage Headroom
5.5
V
Maximum VOUT, Faulted VADJ
23.0
V
VADJ Discharge Device, VOL Operational Current (source)
0.65 -125
V mA
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FN6487.1 August 23, 2007
ISL6720A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2 and "Typical Application" on page 3. 17 V < VPWR < 100V, CVSW = CVCONT = 1F, IVCONT = -250A, IVSW = -500A, VSW Enabled, TA = -40C to +105C (Note 4), Typical values are at TA = +25C (Continued) TEST CONDITIONS VPWR = 17V, 48V VADJ = 15V, VSW Disabled VPWR = 17V, 100V VADJ = 0V, VSWADJ = 0V, VSW Enabled IVIO 1.00mA (Notes 5, 6) VPWR = 100V, VSW Disabled VADJ = 0V, 40V (Note 5) (Note 5) VPWR = 48V IVSW = -500A to -50mA VADJ = 0V, VIO = 22V, 40V ext. VSWADJ = 0.471V VSWADJ = 1.000V VSWADJ = 2.143V Setpoint Range VPWR = 48V, VADJ = 0V, VIO = 40V ext. VSWADJ = 0V VSWADJ = 2.25V Source Voltage Headroom, VIO - VSW VPWR = 21V, VADJ = 0V, VSW = 15V, IVSW = -50mA VIO - VSW VSW final = 0.95 x VSW initial VIO = 17 V ext., VADJ = 0V, VSW = 15V, IVSW = -50mA VPWR - VSW VSW final = 0.95 x VSW initial VPWR = 48V, IVSWADJ = 10mA VSW Disabled, VADJ = 15V VSWADJ = 4V, VIO = 40V, IVSW = -50mA VSW = VADJ*GVSWADJ TA = +125C, 1000 hours, (Note 5) VPWR = 48V, VSWADJ = 1.0V, IVSW = -50mA, VADJ = 0V, VIO = 40V ext. VPWR = 48V, VADJ = 0V VIO = 17V ext., VSWADJ = 2.14V VPWR = 100V, VADJ = 0V VIO = 40V ext. VPWR = 100V, VIO = 40V ext. VSWADJ = 0V, 5V VPWR = 17V, 100V IVCONT = -250A to -25mA VADJ = 0V, VIO = 10V, 40V ext. TA = -40 to +105C -50 -80 -1.0 -225 -300 1.0 15.1 7 0.3 0.10 0 15 1.0 1.5 1.5 V V V -5 -3 -3 +5 +3 +3 % % % 0.1 -75 -25 1 MIN -225 TYP -380 MAX -500 40 UNITS mA V
PARAMETER Current Limit Maximum External Bias
Load Capacitance Range VADJ Bias Current OUTPUT VOLTAGE VSW Load Capacitance Range Compensation Capacitance Overall Accuracy
F A
0.47 180
1.0 220
1.5 260
F pF
Source Voltage Headroom, VPWR - VSW
5.5
V
Minimum Required Load VSWADJ Discharge Device, VOL Maximum VOUT, Faulted VSWADJ VSWADJ DC Gain Long Term Stability
-500 0.25 23
A V V V/V %
Operational Current (source) Current Limit VSWADJ Bias Current OUTPUT VOLTAGE VCONT Overall Accuracy
mA mA A
4.925
5.000
5.075
V
5
FN6487.1 August 23, 2007
ISL6720A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2 and "Typical Application" on page 3. 17 V < VPWR < 100V, CVSW = CVCONT = 1F, IVCONT = -250A, IVSW = -500A, VSW Enabled, TA = -40C to +105C (Note 4), Typical values are at TA = +25C (Continued) TEST CONDITIONS VPWR = 48V, VADJ = 0V VIO biased ext. IVCONT = 0.95 x IVIO + 0.05 x IVPWR IVCONT = -25mA, minimum IVCONT = -5mA, minimum Minimum Required Load Long Term Stability TA = +125C, 1000 hours, (Note 5) VPWR = 100V, VADJ = 0V VSW Disabled, IVCONT = -25mA VPWR = 17V, VADJ = 0V VSW Disabled VPWR = 17V, 100V, VADJ = 0V VIO = 0V, 40V ext., VSW Disabled (Note 5) (Note 5) % of VCONT VPWR = 48V, VSWADJ = 2.14V VADJ = 20V, IVIO = 0mA % of VCONT VPWR = 48V, VSWADJ = 2.14V VADJ = 20V, IVIO = 0mA % of VCONT VPWR = 48V, VSWADJ = 2.14V VADJ = 20V, IVIO = 0mA VENABLE = 0V tVSW, 10% to tENABLE, 60% tVSW, 90% to tENABLE, 40% tVCONT,10% to tVPWR > UVLO, IVCONT = 0A % of VCONT 5 1 150 70 89 200 140 95 45 150 105 45 -25 -30 0.47 800 54 -95 1.0 1000 60 -150 1.5 1200 66 0.2 3.4 3.1 5.0 4.5 -250 V V A % MIN TYP MAX UNITS
PARAMETER Source Voltage Headroom VIO - VCONT
Operational Current (source) Current Limit Output Capacitance Compensation Capacitance ENABLE High Level Input Voltage (VIH)
mA mA F pF %
Low Level Input Voltage (VIL)
34
40
46
%
Hysteresis
16
20
24
%
Pull-Up Resistance Turn-On Delay Turn-Off Delay POR Turn-On Delay POR Threshold, VCONT increasing POR Hysteresis THERMAL PROTECTION Thermal Shutdown 1, VSW off, VIO off Thermal Shutdown 1 Clear Hysteresis 1, Internal Protection Thermal Shutdown 2, VCONT off Thermal Shutdown 2 Clear Hysteresis 2, Internal Protection NOTES:
100 50 15 500 98
k s s s % mV C C C C C C
4. Specifications at -40C and +105C are guaranteed by +25C test with margin limits. 5. Limits established by characterization and are not production tested. 6. The maximum load capacitance is limited only by practical considerations. Large values of capacitance combined with high supply voltage (VPWR) may activate the thermal protection prior to reaching steady state operation.
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FN6487.1 August 23, 2007
ISL6720A Typical Performance Curves
3.5 3.3 3.1 VADJ - VIO (V) 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 0 10 20 30 40 50 60 70 80 90 100 VADJ = 10V VADJ = 20V VADJ = 15V VADJ - VIO (V) 3.5 3.3 3.1 2.9 2.7 VPWR = 48V
2.5 VPWR = 20V 2.3 2.1 1.9 1.7 1.5 0 10 20 30 40 50 60 70 80 90 100 VPWR = 80V
VIO LOAD (mA)
VIO LOAD (mA)
FIGURE 1. VADJ - VIO vs IVIO @ VPWR = 25V, +25C
FIGURE 2. VADJ - VIO vs IVIO @ VADJ = 15V, +25C
1.001 NORMALIZED VCONT TEMPERATURE VARIATION NORMALIZED VSW TEMPERATURE VARIATION
1.002 VSW = 5.0V
1.000
1.001 VSW = 20V 1.000 VSW = 3.3V
0.999
0.998
0.999
VSW = 12V
0.997 -40
-25
-10
5
20
35
50
65
80
95
110
0.998 -40
-25
-10
5
20
35
50
65
80
95
110
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 3. VCONT REGULATION vs TEMPERATURE
FIGURE 4. VSW REGULATION vs TEMPERATURE
Pin Descriptions
VPWR - VPWR is the primary power connection for the IC. The under voltage lockout (UVLO) feature of VPWR enables/disables all outputs even if VIO is externally biased. To optimize noise immunity, bypass VPWR to GND with a ceramic capacitor as close to the VPWR and GND pins as possible. VCONT - A 25mA continuous output that derives its source voltage from either VIO (when enabled and sufficient) or VPWR (when VIO is not available). VCONT sequences on before VIO and VSW by approximately 250s. The over-temperature protection feature protects VCONT at a higher temperature than VIO and VSW. This ensures VIO and VSW shutdown at a lower temperature and allows VCONT to remain on. VCOMP - A 1000pF compensating capacitor is placed between VCOMP and VCONT to stabilize the control loop. This value may vary depending on the output load and capacitance applied between VCONT and GND.
VIO - This is the unswitched low voltage output supply. It may be used as is, or may be back-biased by an auxiliary power source such as a transformer winding. VIO should be bypassed to GND with a 0.1F capacitor. Although a minimum capacitance is not required, it does provide the source voltage bypass for VSW and VCONT when VIO is capable of supporting those outputs. Smaller values of capacitance will result in larger disturbances during load transients. Its output is adjustable from 0V to 20.0V using a reference on VADJ, such as a zener diode and bias resistor. VIO may be soft-started with a capacitance to ground from VADJ. VADJ - The feedback adjustment pin for VIO. An external reference on VADJ sets the voltage on VIO. The reference may be a resistor/zener diode combination from VPWR. VADJ has a discharge device that activates momentarily during power-up and power-down sequences to allow VIO to be soft started. GND - Signal and power ground connections for this device.
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FN6487.1 August 23, 2007
ISL6720A
VSW - This is the switched regulated low voltage output supply derived from VIO. Bypass to GND with a 1.0F capacitor. Its output is adjustable from 0V to 15.0V using an appropriate divider from VCONT to VADJ and GND. VSW is nominally 7 x VSWADJ. Protection circuitry prevents the output from exceeding 23V in the event of a fault on VSWADJ (short high). The minimum output current capability is 50mA with transient capability to > 80mA. VSW may be soft-started by placing a capacitor from VSWADJ to GND. ENABLE - The positive logic on/off control input that controls the VSW output. A logic high enables VSW. VSWCOMP - A 220pF compensating capacitor is placed between VSWCOMP and VSW to stabilize the control loop. This value may vary depending on the output load and capacitance applied between VSW and GND. VSWADJ - The feedback adjustment pin for VSW. A divider from VCONT to GND sets the output voltage for VSW. VSWADJ has a node discharge device that activates momentarily at power-up, when disabled (ENABLE low), and during power-down sequences. VSW is nominally 7 x VSWADJ. on VIO gradually transfers from the VIO regulator to external back-bias source. Depending on load, the back-bias voltage may have to exceed the VIO setpoint by as much as 3V before the VIO regulator is off. The output voltage of VIO is set by applying a reference voltage to VADJ. The reference voltage may be set by using a resistor and zener diode combination from the VPWR input. VIO ranges from 0.5V to 4.5V below the voltage applied to VADJ depending on the load on VIO. VIO can source more than 125mA for short durations, limited only by the device power dissipation and the thermal constraints of the application.
VIO = VADJ - V OFFSET V (EQ. 1)
where VOFFSET ranges from 0.5V to 4.5V.
VIN
1
VPWR
VIO 11 N/C 10
2 3 4 5
VCONT VADJ VCOMP VSW
9 8 7 6
Functional Description
Features
The control circuitry used in Telecom/Datacom DC/DC converters often requires an operating bias voltage significantly lower than the source voltage available to the converter. Many applications use a discrete linear regulator from the input source to create the bias supply. Often an auxiliary winding from the power transformer is used to supplement or replace the linear supply once the converter is operating. The auxiliary winding bias voltage may require regulation, as well, to minimize the voltage variation inherent in unregulated transformer winding outputs. When implemented discretely, this circuitry occupies significant PWB area, a considerable problem in today's high density converters. The ISL6720A triple linear regulator simplifies the start-up and operating bias circuitry needed in Telecom and Datacom DC/DC converters by integrating these functions, and more, in a small 4mmx4mm DFN package.
GND VSWCOMP VSWADJ ENABLE
FIGURE 5. SETPOINT ADJUSTMENT FOR VIO
VIO
VIO is the primary output of the ISL6720A, providing bias voltage whenever the input source voltage, VPWR, is above its under voltage lockout (UVLO) threshold. VIO, which is an abbreviation for "voltage input/output", is adjustable from 0.5V to 20V using the VADJ input, and may be back-biased up to 40V from an external source independent of VPWR. The back-bias voltage must be higher than the VIO setpoint to disable the internal VIO regulator. The transition from internal VIO to external VIO is not abrupt. As the back-bias voltage increases above the VIO setpoint, the load current
VIO may be soft-started using the VADJ input. By limiting the rate of rise of VADJ, the risetime of VIO may be controlled. Soft-start may be accomplished by placing a capacitor to ground from VADJ. The capacitor to ground and the resistor from VPWR determine the RC charging characteristic for the voltage at VADJ. Since VADJ is pulled low at power-up and power-down, soft-start always starts from a known state. The soft-start rate cannot exceed the intrinsic risetime set by the current limit threshold of the output. As load capacitance increases, the intrinsic risetime increases. In general, placing large capacitance values on VIO should be avoided, particularly if the source voltage applied to VPWR is high. Having a large load capacitance and high input voltage results in high power dissipation for a longer duration and may activate the over-temperature protection before VIO can be biased externally. Under such conditions, steady state operation would not be achievable. If the auxiliary transformer winding used to back-bias VIO requires a large value of capacitance, it can be isolated from VIO using a diode as shown in Figure 6.
8
FN6487.1 August 23, 2007
ISL6720A
.
VIO 11 N/C 10 ISL6720A VADJ 9 VSW 8 VSWCOMP 7 ENABLE 6
TRACE 3
+
TRACE TRACE 1 1
FIGURE 6. ISOLATING VIO FROM LARGE CAPACITANCES
TRACE 2
VSW
VSW is the switched output and may be turned on and off using the ENABLE pin (GND = off). The output is adjustable from 1.5V to 15V, but must always be at least 1.5V lower than VIO and 5.5V lower than VPWR. VSW uses VIO as its input source. If the external source applied to VIO is unable to supply adequate voltage, VPWR will be selected as an alternate source for VIO (and VSW). VSW is capable of sourcing up to 50mA continuously, and up to 80mA on a transient basis. The output voltage is adjusted using the VSWADJ input. The voltage applied to this pin, multiplied by an internal gain of 7, sets the output voltage.
VSW = 7 x VSWADJ V (EQ. 2)
TRACE 1
FIGURE 7. VSW TRANSIENT RESPONSE, 0mA to 50mA STEP, TRACE1: VSW, TRACE2: VCONT, TRACE3: VIO
With a 220pF capacitor from VSW to VSWCOMP, the load capacitance on VSW should be 1.0F nominal, with a range of 0.47F to 1.5F. VSW requires a minimum load of 500A. These conditions must be met even if the VSW output is not used.
TRACE 3
VCONT
VCONT, which has a tight tolerance output and can source 25mA, is a continuos output. It remains on during most fault conditions and precedes VIO and VSW during power-up. It may be used as reference for other circuitry, or may be used to power a micro-controller or other similar device. VCONT selects VIO as its primary source voltage, but also uses VPWR if VIO is not present or capable. VIO must have at least 5V of headroom above VCONT or VPWR is selected as the source. VCONT is enabled when VPWR exceeds its UVLO threshold and its operation precedes the enabling of VIO and VSW by 250s, nominal. VCONT requires a minimum 250A load for stability. It should be bypassed to GND with a 1F capacitor and requires a 1nF compensation capacitor between VCOMP and VCONT. These conditions must be met even if the VCONT output is not used.
FIGURE 8. VCONT TRANSIENT RESPONSE, 0mA to 25mA STEP, TRACE1: VSW, TRACE2: VCONT, TRACE3: VIO
TRACE 2
Figure 7 depicts the output deviation on each output when VSW experiences a 0mA to 50 mA step load. VIO Is unloaded without back-bias and VCONT has a 250A (minimum) load. Figure 8 depicts the output deviation on each output when VCONT experiences a 0mA to 25mA step load. VIO Is unloaded without back-bias and VSW has a 500A (minimum) load.
9
FN6487.1 August 23, 2007
ISL6720A
Over-Temperature Protection
The ISL6720A has a two-stage over-temperature shutdown mechanism. VIO and VSW shutdown approximately +10C lower than VCONT. The hysteresis for both thresholds is large so that the IC has sufficient time to operate at start-up loading levels without prematurely re-triggering the over temperature protection. At rated load on each output, a +105C junction temperature, and with VPWR at 80V, the thermal mass combined with the over-temperature thresholds allows approximately 10ms of start-up time.
.
VIN
1 VPWR
VPWR
VPWR provides the source voltage for the IC and load until VIO is back biased. The IC is disabled (all outputs off) when UVLO is active. If the application requires high currents or longer start-up times than the thermal protection allows, the device dissipation may be reduced by adding a resistor or resistors in series between the input voltage and VPWR. The dropping resistance must be selected such that VPWR remains above the UVLO threshold of VPWR and at least 5.5V greater than VIO under maximum load and minimum input voltage to maintain regulation.
2 VCONT 3 VCOMP 4 GND 5 VSWADJ
FIGURE 9. ADDING DROPPING RESISTORS TO VPWR
PWB Layout Requirements
Careful layout is essential for satisfactory operation of the device. In particular, the compensation capacitors must be connected to VCOMP and VSWCOMP with short trace lengths.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6487.1 August 23, 2007
ISL6720A
Package Outline Drawing
L11.4x4
11 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 6/07
2X 2.5 4.00 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 B 1 8X 0.50 1.0 5 11X 0 . 45 0 . 1
4.00
1.58
(4X)
0.15 11 6
TOP VIEW
2.80
0.10 M C A B 0.05 M C 4 0.25
BOTTOM VIEW
( 2.80 ) SEE DETAIL "X"
0.10 C
( 11 X 0.65 ) 0 .9 0.1mm
BASE PLANE
C
SIDE VIEW
( 3.75 ) ( 1.58 ) C 0 . 2 REF
SEATING PLANE 0.08 C
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
( 11 X 0 . 25 ) (8X 0.5)
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
TYPICAL RECOMMENDED LAND PATTERN
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FN6487.1 August 23, 2007

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